Intel’s 10 nm process is not feasible, it could switch to a 12 nm one

Our regular readers know that Intel is having serious issues with the 10 nm process. When the first-gen Core processors came out, Intel adopted a strategy known as “tick tock”, a shrinking of the manufacturing process every two years.

This system would introduce major advances in terms of performance, power consumption and operating temperatures. However, the fact that Intel gave up soldering the IHS had very negative consequences, so the processor temperature did not improve despite the constant size reduction. To understand the situation, we just have to go back to the moment when the change happened: when Ivy Bridge was launched.

Sandy Bridge processors are fabricated on a 32 nm process and Ivy Bridge processors on a 22 nm process. However, Ivy Bridge processors had really high temperatures that were even worse than those of the previous generation. This was a direct consequence of giving up the Sandy Bridge processors’ soldering, which was replaced by thermal paste on Ivy Bridge processors.

Change of architecture and manufacturing process

As we have already said, Intel’s “tick tock” strategy was based on a very simple model: a shrinking in the manufacturing process size one year, and a new architecture the next year. The “tick” represented a shrinking of the process that increased the number of transistors without increasing power consumption. We have already talked about operating temperatures in previous paragraphs. A good example is the leap from Sandy Bridge to Ivy Bridge, as we said above, and the leap from Haswell (22 nm) to Broadwell (14 nm).

The “tock” is a microarchitecture change that increases the processor’s raw performance in terms of IPC, although it can also mean an increase in the core count and operating speeds. A good example is the leap from Ivy Bridge (22 nm) to Haswell (22 nm).

Had that strategy worked, then the only processors fabricated on 14 nm processes would be Broadwell and Skylake. This means that Kaby Lake (14 nm+) and Coffee Lake (14 nm++) should not have hit the market. Cannon Lake (10 nm) and its successor Ice Lake (10 nm+) should have been in their place instead. First there should have been the “tick” for Skylake and then the “tock” for Cannon Lake.

The problems Intel has faced trying to switch to a 10 nm process put an end to the “tick tock” strategy, leaving us with two “refresh” models of the 14 nm process: Kaby Lake and Coffee Lake, and Whiskey Lake (Coffee Lake Refresh) will soon join them. All those names as well as keeping the 14 nm process indicated that Intel’s problems with the 10 nm process were worse than what the brand even recognized. This new report clearly confirms it.

The 10 nm process has a very low success rate

In this article we saw how Intel talked about the 10 nm process as a highly ambitious approach and the extreme ultraviolet lithography to successfully switch to a 7 nm process. This suggests that the company should have taken advantage of said lithography in order to jump to the 10 nm process from the beginning.

Intel has been working on the 10 nm process for years, and it finally has a launch date: 2019. However, the latest reports claim that the original design used for the 10 nm process keeps posing major issues to the point where the success rate is barely around 8%-10%. The acceptable minimum should be around 50%-60%.

This makes the 10 nm process entirely unfeasible both technically and commercially. It would have prompted Intel to radically change the original design, forcing the company to give up the 10 nm process and go for a halfway solution: 12 nm.

We remind you that switching to a new manufacturing process is complicated, but the difficulty level depends on transistor density. In this sense, Intel has always taken a highly ambitious approach that is in turn highly difficult. We will show you a perfect example so you can have a better idea:

  • Intel chip on a 10 nm process: up to 12.8 billion transistors on 127 mm²
  • Apple A11 SoC on a 10 nm process: 3.4 billion transistors on 87.66 mm²